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NXP Semiconductors /MIMXRT1062 /DCDC /REG3

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Interpret as REG3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRG0TARGET_LP 0 (MINPWR_DC_HALFCLK)MINPWR_DC_HALFCLK 0 (MISC_DELAY_TIMING)MISC_DELAY_TIMING 0 (MISC_DISABLEFET_LOGIC)MISC_DISABLEFET_LOGIC 0 (DISABLE_STEP)DISABLE_STEP

Description

DCDC Register 3

Fields

TRG

Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V
TARGET_LP

Target value of standby (low power) mode 0x0: 0
MINPWR_DC_HALFCLK

Set DCDC clock to half freqeuncy for continuous mode
MISC_DELAY_TIMING

Ajust delay to reduce ground noise
MISC_DISABLEFET_LOGIC

Reserved
DISABLE_STEP

Disable stepping for the output VDD_SOC of DCDC

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data